TY - GEN
T1 - A low-cost SVM classifier on FPGA for pedestrian detection
AU - Ngo, Vinh
AU - Casadevall, Arnau
AU - Codina, Marc
AU - Castells-Rufas, David
AU - Carrabina, Jordi
PY - 2018
Y1 - 2018
N2 - Support Vector Machine (SVM) classifier is an intensive computational part of a pedestrian detection system. A real-time system requires the classifier to be implemented in embedded platforms. In this paper, a hardware accelerator for the SVM classifier, which is part of the pedestrian detection system, has been designed and implemented on FPGA. The accelerator, which targets low latency and on-chip memory use, can be scaled to different input image sizes. The memory usage of the accelerator alone is 77% of the state of the art implementation. The accelerator is demonstrated by being integrated into a pedestrian detection. It increases the system’s throughput by 1.9 times.
AB - Support Vector Machine (SVM) classifier is an intensive computational part of a pedestrian detection system. A real-time system requires the classifier to be implemented in embedded platforms. In this paper, a hardware accelerator for the SVM classifier, which is part of the pedestrian detection system, has been designed and implemented on FPGA. The accelerator, which targets low latency and on-chip memory use, can be scaled to different input image sizes. The memory usage of the accelerator alone is 77% of the state of the art implementation. The accelerator is demonstrated by being integrated into a pedestrian detection. It increases the system’s throughput by 1.9 times.
UR - https://zenodo.org/record/2421944
U2 - 10.5281/zenodo.2421944
DO - 10.5281/zenodo.2421944
M3 - Other contribution
ER -