A general purpose computer emulator

Emilio Luque Fadon, Lorenzo Moreno Ruiz, JoséF Tirado Fernandez

    Research output: Contribution to journalArticleResearchpeer-review


    The emulator is organized as a set of four asynchronous units which carry out specific functions and which can work in a concurrent form. This units are: The Master Control, the Instruction Management, the Memory and the Data Management. The master control distributes the jobs that each unit should accomplish. The processor communication system is based in the Dijkstra's binary semaphore concept. In order to simplify the microinterpreters construction, the emulator has the following features: 1) A flexible and reformable structure with a variable length of processing; 2) A decoding and field extraction mechanism for the instructions, based on an associative memory, a barrel shifter and a mask circuit; 3) A microinstruction set with a high-level semantic. © 1978.
    Original languageEnglish
    Pages (from-to)133-140
    JournalJournal of Systems Architecture
    Publication statusPublished - 1 Jan 1978


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