Original language | English |
---|---|
Title of host publication | Proceedings ED&TC European Design and Test Conference |
Place of Publication | Los Alamitos (US) |
Pages | 609-609 |
Edition | 1 |
DOIs | |
Publication status | Published - 1 Jan 1996 |
A combined pairing and chaining algorithm for CMOS layout generation
A. J. Velasco, X. Marin, R. P. Llopis, J. Carrabina
Research output: Chapter in Book › Chapter › Research