A combined pairing and chaining algorithm for CMOS layout generation

A. J. Velasco, X. Marin, R. P. Llopis, J. Carrabina, 10.1109/EDTC.1996.494373 doi: (Editor)

    Research output: Chapter in BookChapterResearch

    Original languageEnglish
    Title of host publicationProceedings ED&TC European Design and Test Conference
    Place of PublicationLos Alamitos (US)
    Pages609-609
    Edition1
    Publication statusPublished - 1 Jan 1996

    Cite this

    Velasco, A. J., Marin, X., Llopis, R. P., Carrabina, J., & doi:, . EDTC. . . (Ed.) (1996). A combined pairing and chaining algorithm for CMOS layout generation. In Proceedings ED&TC European Design and Test Conference (1 ed., pp. 609-609).