A combined pairing and chaining algorithm for CMOS layout generation

A. J. Velasco, X. Marin, R. P. Llopis, J. Carrabina, 10.1109/EDTC.1996.494373 doi: (Editor)

    Research output: Chapter in BookChapterResearch

    Original languageEnglish
    Title of host publicationProceedings ED&TC European Design and Test Conference
    Place of PublicationLos Alamitos (US)
    Pages609-609
    Edition1
    Publication statusPublished - 1 Jan 1996

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