A combined pairing and chaining algorithm for CMOS layout generation

A. J. Velasco, X. Marin, R. P. Llopis, J. Carrabina

Research output: Chapter in Book › Chapter › Research

Original language	English
Title of host publication	Proceedings ED&TC European Design and Test Conference
Place of Publication	Los Alamitos (US)
Pages	609-609
Edition	1
DOIs	https://doi.org/10.1109/EDTC.1996.494373
Publication status	Published - 1 Jan 1996

Access to Document

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title = "A combined pairing and chaining algorithm for CMOS layout generation",

author = "Velasco, {A. J.} and X. Marin and Llopis, {R. P.} and J. Carrabina",

year = "1996",

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doi = "10.1109/EDTC.1996.494373",

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booktitle = "Proceedings ED&TC European Design and Test Conference",

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T1 - A combined pairing and chaining algorithm for CMOS layout generation

AU - Velasco, A. J.

AU - Marin, X.

AU - Llopis, R. P.

AU - Carrabina, J.

PY - 1996/1/1

Y1 - 1996/1/1

U2 - 10.1109/EDTC.1996.494373

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BT - Proceedings ED&TC European Design and Test Conference

CY - Los Alamitos (US)

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