A combined pairing and chaining algorithm for CMOS layout generation

A. J. Velasco, X. Marin, R. P. Llopis, J. Carrabina, 10.1109/EDTC.1996.494373 doi: (Editor)

Research output: Chapter in Book › Chapter › Research

Original language	English
Title of host publication	Proceedings ED&TC European Design and Test Conference
Place of Publication	Los Alamitos (US)
Pages	609-609
Edition	1
Publication status	Published - 1 Jan 1996

Cite this

Velasco, A. J., Marin, X., Llopis, R. P., Carrabina, J., & doi:, . EDTC. . . (Ed.) (1996). A combined pairing and chaining algorithm for CMOS layout generation. In Proceedings ED&TC European Design and Test Conference (1 ed., pp. 609-609).

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title = "A combined pairing and chaining algorithm for CMOS layout generation",

author = "Velasco, {A. J.} and X. Marin and Llopis, {R. P.} and J. Carrabina and 10.1109/EDTC.1996.494373 doi:",

year = "1996",

month = jan,

day = "1",

language = "English",

isbn = "9780818670398",

pages = "609--609",

booktitle = "Proceedings ED&TC European Design and Test Conference",

edition = "1",

}