To continue with the exponential improvement of integrated circuit performance, the continuous scaling of MOSFET dimensions and operating voltages is required. In this project we will study several important issues related to this scaling process for transistor lenght ranging from 100 nm (the next technology node) down to the limit of 10nm. We will deal with some issues related to electron transport and MOSFET simulation, performance evaluation, compact modelling and reliability. We will focus the attention in the double-gate MOSFET topology, which is considered to be one convenient alternative for the sub-100 nm regime. In the field of electron transport, we will mainly study dynamic properties such as high-frequency behaviour and noise usin quantum Monte Carlo simulation. We will start by the simulation of noise in 1D heterostructure devices using exact Bohm trajectories and we will develop an approximate model to deal with the case of 2D transport in the MOSFET. As far as performance evaluation, we will focus the attention on analog and high-frequency applications, suggesting a MOSFET design to meet the specifications required by the International Technology Roadmap for Semiconductors (ITRS) for "Mixed Signal Systems", and studying figures of merit of analog sub-circuits of critical importance. As one of the results of MOSFET simulation, we will develop a physics-based compact model based on Landauer formulation of transport, Finally, we will study MOSFET reliability for devices with oxide thickness between 1 nm and 2nm, considering the main failure mechanisms (dielectric breakdown and degradation of threshold voltage), defining device failure criteria and developing a flexible reliability methodology. This methodology should allow the qualification of technology and, at the same time, be adequate to reliability assurance of different circuits applications (both digital and analog).
|Effective start/end date||1/12/03 → 30/11/06|