In order to continuewith the exponential improvement of integrated circuit performance, the continuos scaling of MOSFET dimensions and operating voltages is required. In this project we will study several important issues related to this scaling process for transistor length ranging from 100 nm (the next technology node) down to the limit of 10nm. We will deal with some issues related to electron transport and MOSFET simulation, performance evaluation, compact modelling and reliability. We will focus the attention in the double-gate (DG) and stained Si/SiGe MOSFET topology, which is considered to be potential candidates for next generation complementary CMOS devices (...)
|Effective start/end date||1/01/05 → 31/12/06|
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