Fiabilitat de l'òxid de porta de dispositius MOS: efectes en el funcionament de dispositius i circuits

  • Nafria Maqueda, Montserrat (Principal Investigator)
  • Aguilera Martínez, Lídia (Researcher on contract)
  • Blasco Jimenez, Francisco Javier (Researcher on contract)
  • Fernández García, Raúl (Researcher on contract)
  • Porti Pujal, Marc (Researcher on contract)
  • Rodriguez Martinez, Rosana (Researcher on contract)
  • Aymerich Humet, Francisco Javier (Investigator)

Project Details


The main objective of the proposed project is the analysis of the effect of the degradation and dielectric breakdown (BD) of the gate oxide (SiO2) on the performance of microelectronic devices and circuits. The project can be located in a context where the reliability of the gate oxide has become one of the most important limiting factors for the future scaling of microelectronics technology in its present form. Recent works have shown that the oxide failure does not necessarily imply the device and circuit failures, so that it has been pointed out that the reliability requirements imposed for the gate oxide can be too restrictive. Therefore, the knowledge of the real susceptibility of circuits to the oxide failure is mandatory. In this project, this susceptibility will be analysed, both at device and circuit level. As far as the device is concerned, we will carry out an analysis of the effect of BD on the device circuit parameters, with the aim of developing models that can be implemented in a circuit simulator. It should be taken into account that the characterization needed to get these parameters should be done under stress conditions as closer as possible to those present during the operation of the device in a circuit. Concerning circuits, the effect of BD on their performance will be experimentally determined. Moreover, the circuits will be simulated, including the BD models for the devices developed from the previous device characterization. The comparison of the results obtained from the circuit characterization and simulation stages will allow to validate (or refine) the developed models. The availability of models for the device failure (implementable in a circuit simulator), that can be used by circuit designers, can help to the development of fault tolerant circuits, which could extend the presence of SiO2 as gate dielectric in CMOS technologies.
Effective start/end date1/12/0330/11/06


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