Trapped charge and stress induced leakage current (SILC) in tunnel SiO<inf>2</inf> layers of de-processed MOS non-volatile memory devices observed at the nanoscale

M. Lanza, M. Porti, M. Nafría, X. Aymerich, G. Ghidini, A. Sebastiani

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Resum

In this work, Conductive Atomic Force Microscope (CAFM) experiments have been combined with device level measurements to evaluate the impact of an electrical stress applied on MOS structures with a 9.8 nm thick SiO2 layer for memory devices. Charge trapping in the generated defects and leakage current measured at the nanoscale have been correlated to the measurements obtained on fully processed MOS structures. Crown Copyright © 2009.
Idioma originalEnglish
Pàgines (de-a)1188-1191
RevistaMicroelectronics Reliability
Volum49
DOIs
Estat de la publicacióPublicada - 1 de set. 2009

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