Trapped charge and stress induced leakage current (SILC) in tunnel SiO<inf>2</inf> layers of de-processed MOS non-volatile memory devices observed at the nanoscale

M. Lanza; A. Sebastiani; M. Nafría; M. Porti; G. Ghidini; X. Aymerich

doi:10.1016/j.microrel.2009.06.016

Trapped charge and stress induced leakage current (SILC) in tunnel SiO<inf>2</inf> layers of de-processed MOS non-volatile memory devices observed at the nanoscale

M. Lanza, A. Sebastiani, M. Nafría, M. Porti, G. Ghidini, X. Aymerich

Departament d'Enginyeria Electrònica

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In this work, Conductive Atomic Force Microscope (CAFM) experiments have been combined with device level measurements to evaluate the impact of an electrical stress applied on MOS structures with a 9.8 nm thick SiO2 layer for memory devices. Charge trapping in the generated defects and leakage current measured at the nanoscale have been correlated to the measurements obtained on fully processed MOS structures. Crown Copyright © 2009.

Idioma original	Anglès
Pàgines (de-a)	1188-1191
Revista	Microelectronics Reliability
Volum	49
DOIs	https://doi.org/10.1016/j.microrel.2009.06.016
Estat de la publicació	Publicada - 1 de set. 2009

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10.1016/j.microrel.2009.06.016

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title = "Trapped charge and stress induced leakage current (SILC) in tunnel SiO2 layers of de-processed MOS non-volatile memory devices observed at the nanoscale",

abstract = "In this work, Conductive Atomic Force Microscope (CAFM) experiments have been combined with device level measurements to evaluate the impact of an electrical stress applied on MOS structures with a 9.8 nm thick SiO2 layer for memory devices. Charge trapping in the generated defects and leakage current measured at the nanoscale have been correlated to the measurements obtained on fully processed MOS structures. Crown Copyright {\textcopyright} 2009.",

author = "M. Lanza and A. Sebastiani and M. Nafr{\'i}a and M. Porti and G. Ghidini and X. Aymerich",

year = "2009",

month = sep,

day = "1",

doi = "10.1016/j.microrel.2009.06.016",

language = "English",

volume = "49",

pages = "1188--1191",

journal = "Microelectronics Reliability",

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publisher = "Elsevier Limited",

}

Trapped charge and stress induced leakage current (SILC) in tunnel SiO<inf>2</inf> layers of de-processed MOS non-volatile memory devices observed at the nanoscale. / Lanza, M.; Sebastiani, A.; Nafría, M. et al.
In: Microelectronics Reliability, Vol. 49, 01.09.2009, pàg. 1188-1191.

Producció científica: Contribució a revista › Article › Recerca › Avaluat per experts

TY - JOUR

T1 - Trapped charge and stress induced leakage current (SILC) in tunnel SiO2 layers of de-processed MOS non-volatile memory devices observed at the nanoscale

AU - Lanza, M.

AU - Sebastiani, A.

AU - Nafría, M.

AU - Porti, M.

AU - Ghidini, G.

AU - Aymerich, X.

PY - 2009/9/1

Y1 - 2009/9/1

N2 - In this work, Conductive Atomic Force Microscope (CAFM) experiments have been combined with device level measurements to evaluate the impact of an electrical stress applied on MOS structures with a 9.8 nm thick SiO2 layer for memory devices. Charge trapping in the generated defects and leakage current measured at the nanoscale have been correlated to the measurements obtained on fully processed MOS structures. Crown Copyright © 2009.

AB - In this work, Conductive Atomic Force Microscope (CAFM) experiments have been combined with device level measurements to evaluate the impact of an electrical stress applied on MOS structures with a 9.8 nm thick SiO2 layer for memory devices. Charge trapping in the generated defects and leakage current measured at the nanoscale have been correlated to the measurements obtained on fully processed MOS structures. Crown Copyright © 2009.

UR - https://dialnet.unirioja.es/servlet/articulo?codigo=3052804

U2 - 10.1016/j.microrel.2009.06.016

DO - 10.1016/j.microrel.2009.06.016

M3 - Article

SN - 0026-2714

VL - 49

SP - 1188

EP - 1191

JO - Microelectronics Reliability

JF - Microelectronics Reliability

ER -

Trapped charge and stress induced leakage current (SILC) in tunnel SiO<inf>2</inf> layers of de-processed MOS non-volatile memory devices observed at the nanoscale

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