TY - JOUR
T1 - Modeling in Verilog-AMS of a front-end for the design of a multichannel readout ASIC for Si microstrips
AU - Montiel, Andreu
AU - Casanova, Raimon
AU - Dieguez, Angel
PY - 2012/10/25
Y1 - 2012/10/25
N2 - Verilog-AMS is used to model the analog front-end of one channel in a multichannel readout ASIC for Silicon microstrips. The modellization in a behavioral language allowed to extract the requirements of the main components of the channel whithout needing to make the design at transistor level, thus decreasing the design time. This model of a complete channel will be used for further integration with the digital proces-sign electronics of the multichannel ASIC.
AB - Verilog-AMS is used to model the analog front-end of one channel in a multichannel readout ASIC for Silicon microstrips. The modellization in a behavioral language allowed to extract the requirements of the main components of the channel whithout needing to make the design at transistor level, thus decreasing the design time. This model of a complete channel will be used for further integration with the digital proces-sign electronics of the multichannel ASIC.
UR - http://www.scopus.com/inward/record.url?scp=84870581769&partnerID=8YFLogxK
U2 - 10.1109/SMACD.2012.6339442
DO - 10.1109/SMACD.2012.6339442
M3 - Article
AN - SCOPUS:84870581769
SP - 161
EP - 164
JO - 2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2012
JF - 2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2012
ER -