Modeling in Verilog-AMS of a front-end for the design of a multichannel readout ASIC for Si microstrips

Andreu Montiel*, Raimon Casanova, Angel Dieguez

*Autor corresponent d’aquest treball

Producció científica: Contribució a revistaArticleRecercaAvaluat per experts

1 Citació (Scopus)

Resum

Verilog-AMS is used to model the analog front-end of one channel in a multichannel readout ASIC for Silicon microstrips. The modellization in a behavioral language allowed to extract the requirements of the main components of the channel whithout needing to make the design at transistor level, thus decreasing the design time. This model of a complete channel will be used for further integration with the digital proces-sign electronics of the multichannel ASIC.

Idioma originalAnglès
Pàgines (de-a)161-164
Nombre de pàgines4
Revista2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2012
DOIs
Estat de la publicacióPublicada - 25 d’oct. 2012

Fingerprint

Navegar pels temes de recerca de 'Modeling in Verilog-AMS of a front-end for the design of a multichannel readout ASIC for Si microstrips'. Junts formen un fingerprint únic.

Com citar-ho