Intrinsic noise in aggressively scaled field-effect transistors

According to roadmap projections, nanoscale field-effect transistors (FETs) with channel lengths below 30nm and several gates (for improving their gate control over the source-drain conductance) will come to the market in the next few years. However, few studies deal with the noise performance of these aggressively scaled FETs. In this work, a study of the effect of the intrinsic (thermal and shot) noise of such FETs on the performance of an analog amplifier and a digital inverter is carried out by means of numerical simulations with a powerful Monte Carlo (quantum) simulator. The numerical data indicate important drawbacks in the noise performance of aggressively scaled FETs that could invalidate roadmap projections as regards analog and digital applications. © 2009 IOP Publishing Ltd.