Functional Verification of a RISC-V Vector Accelerator

Victor Jimenez; Mario Rodriguez; Marc Dominguez; Josep Sans; Ivan Diaz; Luca Valente; Vito Luca Guglielmi; Josue V. Quiroga; R. Ignacio Genovese; Nehir Sonmez; Oscar Palomar; Miquel Moreto

doi:10.1109/MDAT.2022.3226709

Functional Verification of a RISC-V Vector Accelerator

Victor Jimenez, Mario Rodriguez, Marc Dominguez, Josep Sans, Ivan Diaz, Luca Valente, Vito Luca Guglielmi, Josue V. Quiroga, R. Ignacio Genovese, Nehir Sonmez, Oscar Palomar, Miquel Moreto

Barcelona Supercomputing Center - Centro Nacional de Supercomputación

Producció científica: Contribució a revista › Article › Recerca › Avaluat per experts

5 Cites (Scopus)

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Editor’s notes: With the mounting interest in the public domain RISC-V instruction set architecture the complexity of verification on RISC-V CPUs is at the forefront. Every RISC-V implementation must ensure it fully complies with the programmer’s manual, independent of the purpose of the program or the application. This article describes a reusable and extendable UVM environment to check the correctness of the executed instructions with a high degree of precision. —Vivek Chickermane, Cadence

Idioma original	Anglès
Pàgines (de-a)	36-44
Nombre de pàgines	9
Revista	IEEE Design and Test
Volum	40
Número	3
DOIs	https://doi.org/10.1109/MDAT.2022.3226709
Estat de la publicació	Publicada - 20 de des. 2022

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10.1109/MDAT.2022.3226709

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title = "Functional Verification of a RISC-V Vector Accelerator",

abstract = "Editor{\textquoteright}s notes: With the mounting interest in the public domain RISC-V instruction set architecture the complexity of verification on RISC-V CPUs is at the forefront. Every RISC-V implementation must ensure it fully complies with the programmer{\textquoteright}s manual, independent of the purpose of the program or the application. This article describes a reusable and extendable UVM environment to check the correctness of the executed instructions with a high degree of precision. —Vivek Chickermane, Cadence",

keywords = "coverage, random binary generation, RISC-V, UVM, vector accelerator, verification",

author = "Victor Jimenez and Mario Rodriguez and Marc Dominguez and Josep Sans and Ivan Diaz and Luca Valente and Guglielmi, \{Vito Luca\} and Quiroga, \{Josue V.\} and Genovese, \{R. Ignacio\} and Nehir Sonmez and Oscar Palomar and Miquel Moreto",

year = "2022",

month = dec,

day = "20",

doi = "10.1109/MDAT.2022.3226709",

language = "English",

volume = "40",

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journal = "IEEE Design and Test",

issn = "2168-2356",

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T1 - Functional Verification of a RISC-V Vector Accelerator

AU - Jimenez, Victor

AU - Rodriguez, Mario

AU - Dominguez, Marc

AU - Sans, Josep

AU - Diaz, Ivan

AU - Valente, Luca

AU - Guglielmi, Vito Luca

AU - Quiroga, Josue V.

AU - Genovese, R. Ignacio

AU - Sonmez, Nehir

AU - Palomar, Oscar

AU - Moreto, Miquel

PY - 2022/12/20

Y1 - 2022/12/20

N2 - Editor’s notes: With the mounting interest in the public domain RISC-V instruction set architecture the complexity of verification on RISC-V CPUs is at the forefront. Every RISC-V implementation must ensure it fully complies with the programmer’s manual, independent of the purpose of the program or the application. This article describes a reusable and extendable UVM environment to check the correctness of the executed instructions with a high degree of precision. —Vivek Chickermane, Cadence

AB - Editor’s notes: With the mounting interest in the public domain RISC-V instruction set architecture the complexity of verification on RISC-V CPUs is at the forefront. Every RISC-V implementation must ensure it fully complies with the programmer’s manual, independent of the purpose of the program or the application. This article describes a reusable and extendable UVM environment to check the correctness of the executed instructions with a high degree of precision. —Vivek Chickermane, Cadence

KW - coverage

KW - random binary generation

KW - RISC-V

KW - UVM

KW - vector accelerator

KW - verification

UR - https://www.scopus.com/pages/publications/85146217381

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DO - 10.1109/MDAT.2022.3226709

M3 - Article

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SN - 2168-2356

VL - 40

SP - 36

EP - 44

JO - IEEE Design and Test

JF - IEEE Design and Test

IS - 3

ER -

Functional Verification of a RISC-V Vector Accelerator

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