TY - JOUR
T1 - Functional Verification of a RISC-V Vector Accelerator
AU - Jimenez, Victor
AU - Rodriguez, Mario
AU - Dominguez, Marc
AU - Sans, Josep
AU - Diaz, Ivan
AU - Valente, Luca
AU - Guglielmi, Vito Luca
AU - Quiroga, Josue V.
AU - Genovese, R. Ignacio
AU - Sonmez, Nehir
AU - Palomar, Oscar
AU - Moreto, Miquel
PY - 2022/12/20
Y1 - 2022/12/20
N2 - Editor’s notes: With the mounting interest in the public domain RISC-V instruction set architecture the complexity of verification on RISC-V CPUs is at the forefront. Every RISC-V implementation must ensure it fully complies with the programmer’s manual, independent of the purpose of the program or the application. This article describes a reusable and extendable UVM environment to check the correctness of the executed instructions with a high degree of precision. —Vivek Chickermane, Cadence
AB - Editor’s notes: With the mounting interest in the public domain RISC-V instruction set architecture the complexity of verification on RISC-V CPUs is at the forefront. Every RISC-V implementation must ensure it fully complies with the programmer’s manual, independent of the purpose of the program or the application. This article describes a reusable and extendable UVM environment to check the correctness of the executed instructions with a high degree of precision. —Vivek Chickermane, Cadence
KW - coverage
KW - random binary generation
KW - RISC-V
KW - UVM
KW - vector accelerator
KW - verification
UR - https://www.scopus.com/pages/publications/85146217381
U2 - 10.1109/MDAT.2022.3226709
DO - 10.1109/MDAT.2022.3226709
M3 - Article
AN - SCOPUS:85146217381
SN - 2168-2356
VL - 40
SP - 36
EP - 44
JO - IEEE Design and Test
JF - IEEE Design and Test
IS - 3
ER -