TY - JOUR
T1 - Digital neural network system based in new concepts on the recall phase dynamics
AU - Carrabina, J.
AU - Calderon, J. C.
AU - Lisa, F.
AU - Perez, C.
AU - Garrido, F.
AU - Avellana, N.
AU - Valderrama, E.
PY - 1992/1/1
Y1 - 1992/1/1
N2 - In this paper we present an electronic system designed to emulate neural networks. Two major restrictions are assumed: discrete synapses (+1,0,-1) and threshold-type neurons. Drawbacks given by restrictions are solved with a more complex learning algorithm that maps real valued configurations for synapses into bipolar ones. The central unit of the system is an ASIC designed in accordance with a new sequential dynamics, which is faster and with better recall characteristics. As a result, the system designed has a fast recall phase and a large number of neurons. A handwritten OCR system is being designed. © 1992.
AB - In this paper we present an electronic system designed to emulate neural networks. Two major restrictions are assumed: discrete synapses (+1,0,-1) and threshold-type neurons. Drawbacks given by restrictions are solved with a more complex learning algorithm that maps real valued configurations for synapses into bipolar ones. The central unit of the system is an ASIC designed in accordance with a new sequential dynamics, which is faster and with better recall characteristics. As a result, the system designed has a fast recall phase and a large number of neurons. A handwritten OCR system is being designed. © 1992.
UR - https://www.scopus.com/pages/publications/0026820368
U2 - 10.1016/0165-6074(92)90109-K
DO - 10.1016/0165-6074(92)90109-K
M3 - Article
SN - 0165-6074
VL - 34
SP - 89
EP - 92
JO - Microprocessing and Microprogramming
JF - Microprocessing and Microprogramming
ER -