Accelerating BWA Aligner Using Multistage Data Parallelization on Multicore and Manycore Architectures

Miquel Angel Senar Rosell; Shaolong Chen

doi:10.1016/j.procs.2016.05.544

Accelerating BWA Aligner Using Multistage Data Parallelization on Multicore and Manycore Architectures

Miquel Angel Senar Rosell, Shaolong Chen

Departament d'Arquitectura de Computadors i Sistemes Operatius

Universitat Autònoma de Barcelona (UAB)

Producció científica: Capítol de llibre › Capítol › Recerca › Avaluat per experts

Idioma original	English
Títol de la publicació	Procedia Computer Science (Proc, International Conference on Computational Science, ICCS 2016)
Subtítol de la publicació	Proc. International Conference on Computational Science 2016, (ICCS 2016)
Lloc de publicació	(NL)
Editor	Elsevier
Pàgines	2438-2442
Nombre de pàgines	4
Volum	80
Edició	1
DOIs	https://doi.org/10.1016/j.procs.2016.05.544
Estat de la publicació	Publicada - 1 de gen. 2016

Accés al document

10.1016/j.procs.2016.05.544

Altres arxius i enllaços

https://www.scopus.com/inward/record.uri?eid=2-s2.0-84978540095&doi=10.1016%2fj.procs.2016.05.544&partnerID=40&md5=5aa8e22dadfd0e0b551984ae5111b47f

Com citar-ho

Senar Rosell, M. A., & Chen, S. (2016). Accelerating BWA Aligner Using Multistage Data Parallelization on Multicore and Manycore Architectures. In Procedia Computer Science (Proc, International Conference on Computational Science, ICCS 2016): Proc. International Conference on Computational Science 2016, (ICCS 2016) (1 ed., Vol. 80, pàg. 2438-2442). Elsevier. https://doi.org/10.1016/j.procs.2016.05.544

Senar Rosell, Miquel Angel ; Chen, Shaolong. / Accelerating BWA Aligner Using Multistage Data Parallelization on Multicore and Manycore Architectures. Procedia Computer Science (Proc, International Conference on Computational Science, ICCS 2016): Proc. International Conference on Computational Science 2016, (ICCS 2016). Vol. 80 1. ed. (NL) : Elsevier, 2016. pàg. 2438-2442

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Senar Rosell, MA & Chen, S 2016, Accelerating BWA Aligner Using Multistage Data Parallelization on Multicore and Manycore Architectures. in Procedia Computer Science (Proc, International Conference on Computational Science, ICCS 2016): Proc. International Conference on Computational Science 2016, (ICCS 2016). 1 ed., vol. 80, Elsevier, (NL), pàg. 2438-2442. https://doi.org/10.1016/j.procs.2016.05.544

Accelerating BWA Aligner Using Multistage Data Parallelization on Multicore and Manycore Architectures. / Senar Rosell, Miquel Angel; Chen, Shaolong.
Procedia Computer Science (Proc, International Conference on Computational Science, ICCS 2016): Proc. International Conference on Computational Science 2016, (ICCS 2016). Vol. 80 1. ed. (NL): Elsevier, 2016. pàg. 2438-2442.

Producció científica: Capítol de llibre › Capítol › Recerca › Avaluat per experts

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Senar Rosell MA, Chen S. Accelerating BWA Aligner Using Multistage Data Parallelization on Multicore and Manycore Architectures. In Procedia Computer Science (Proc, International Conference on Computational Science, ICCS 2016): Proc. International Conference on Computational Science 2016, (ICCS 2016). 1 ed. Vol. 80. (NL): Elsevier. 2016. pàg. 2438-2442 doi: 10.1016/j.procs.2016.05.544