A transistor array chip for the statistical characterization of process variability, RTN and BTI/CHC aging

J. Diaz-Fortuny, J. Martin-Martinez, R. Rodriguez, M. Nafria, R. Castro-Lopez, E. Roca, F.V. Fernandez, E. Barajas, X. Aragones, D. Mateo

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Resum

In this work, a CMOS transistor array is presented, which allows performing process variability, Random Telegraph Noise and BTI/CHC aging characterization in a single chip. The array, called ENDURANCE, integrates 3136 MOS transistors, for single and massive electrical testing. This chip, together with a dedicated measurement set-up, allows programming any of these electrical tests, considerably reducing the total time needed for aging measurements by using a parallelization technique.
Idioma originalEnglish
Nombre de pàgines4
ISBN (electrònic)978-1-5090-5052-9
DOIs
Estat de la publicacióPublicada - 2017

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