A low-cost SVM classifier on FPGA for pedestrian detection

Vinh Ngo, Arnau Casadevall, Marc Codina, David Castells-Rufas, Jordi Carrabina

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Support Vector Machine (SVM) classifier is an intensive computational part of a pedestrian detection system. A real-time system requires the classifier to be implemented in embedded platforms. In this paper, a hardware accelerator for the SVM classifier, which is part of the pedestrian detection system, has been designed and implemented on FPGA. The accelerator, which targets low latency and on-chip memory use, can be scaled to different input image sizes. The memory usage of the accelerator alone is 77% of the state of the art implementation. The accelerator is demonstrated by being integrated into a pedestrian detection. It increases the system’s throughput by 1.9 times.
Idioma originalEnglish
Estat de la publicacióPublicada - 2018

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